(1) Field of the Invention
The present invention relates to a technique of effecting a control of data transfer in, for example, a bus bridge and the like.
(2) Description of Related Art
Recently, input/output (I/O) devices conforming to high-speed communication standard such as gigabit Ethernet and fiber channel have been accepted. To keep pace with this, information-processing devices also require the improvement of the data transfer performance in, for example, bus bridge for effecting data transfer between I/O bus and memory bus.
FIG. 14 schematically shows a configuration of a conventional bus bridge; and FIG. 15 schematically shows a configuration of an information-processing device equipped with the bus bridge. An information-processing device 100 shown in FIG. 15 includes central processing units (CPUs) 21-1 and 21-2, system controllers 23-1 and 23-2, bus bridges 20-1 and 20-2, a cross bar switch 24, memories 22-1, 22-2, 22-3 and 22-4 and I/O devices 25.
To the system controller 23-1, the CPU 21-1, the memories 22-1 and 22-2 and the cross bar switch 24 are connected; also to the system controller 23-2, the CPU 21-2, the memories 22-3 and 22-4 and the cross bar switch 24 are connected, respectively.
To the bus bridges 20-l and 20-2, two I/O devices 25 are connected via an I/O bus 26 respectively; and these bus bridges 20-1 and 20-2 are connected to the cross bar switch 24 via a memory bus 27 respectively.
That is, each of the system controllers 23-1 and 23-2 is connected to the bus bridge 20-1, 20-2 respectively via the cross bar switch 24 so as to be capable of communicating therebetween.
Hereinafter, as for the reference numeral indicating the bus bridge, when one of plural bus bridges has to be specified, reference numerals 20-1 and 20-2 will be used; but when an arbitrary bus bridge is indicated, reference numeral 20 will be used.
As shown in FIG. 14, between the I/O devices 25 and the cross bar switch 24, the bus bridges (memory I/O bus bridges) 20 are disposed between the I/O buses 26 and the memory buses 27, and are arranged in such a manner as to transfer data between these I/O buses 26 and the memory buses 27 of which protocols such as clock frequency and data length of the data to be transferred are different from each other.
In the information processing device 100 equipped with the conventional bus bridges 20, the memory bus 27 includes a write data signal line 27b through which write data and request (address) for writing the data in the memories 22-1 to 22-4 are transmitted and a read data signal line 27a through which read data read out from the memories 22-1 to 22-4 are transmitted. Also, the I/O bus 26 includes an I/O reception signal line 26a for receiving data from the I/O devices 25 and an I/O transmission signal line 26b for transmitting data to the I/O devices 25.
As shown in FIG. 14, the conventional bus bridge 20 includes a transmission buffer 201, a reception buffer 202 and a control information table 203.
The transmission buffer 201 is adapted for temporarily storing the data read out from the memories 22-1 to 22-4 to carry out direct memory access (DMA) read. To the transmission buffer 201, an I/O transmission signal line 26b and a read data signal line 27a are connected so as to be capable of communicating therebetween, and the arrangement is made such that the data from the memories 22-1 to 22-4 are stored in the transmission buffer 201 via the read data signal line 27a, and the read data stored in the transmission buffer 201 are transmitted to the I/O devices 25 via the I/O transmission signal line 27b. 
The reception buffer 202 is adapted for temporarily storing the data to be written in the memories 22-1 to 22-4 to carry out DMA write. To the reception buffer 202, an I/O reception signal line 26a and a write data signal line 27b are connected so as to be capable of communicating therebetween. And the arrangement is made such that the data from the I/O devices 25 are stored in the reception buffer 202; and based on the control information stored in the control information table 203, the data stored in the reception buffer 202 are transmitted to the memories 22-1 to 22-4 as the write data via the write data signal line 27b. 
That is, in the conventional bus bridge 20, as shown in FIG. 14, the memory bus 27 and the I/O bus 26 commonly use the transmission buffer 201 and the reception buffer 202. Also, the memory bus 27 is arranged such that the request and the data are transmitted via the same write data signal line 27b. In the memory bus 27, the request and the data are processed as the same packet. In the event of processing a plurality of memory requests at the same time, the in-order execution in terms of the pertinent process is performed.
The transmission buffer 201 and the reception buffer 202 are arranged such that the data are stored and read out in a manner of first-in first-out (FIFO).
The control information table 203 is adapted for controlling the access to the memories 22-1 to 22-4. The control information table 203 is adapted for effecting a control for transmitting request to the memories 22-1 to 22-4, reading out the read data to be stored in the transmission buffer 201, transmitting the write data stored in the reception buffer 202 to the memories 22-1 to 22-4 and the like.
The conventional bus bridge 20 configured as described above transmits the data from the I/O devices 25 to the memories 22-1 to 22-4 and transmits the data stored in the memories 22-1 to 22-4 to the I/O devices 25; thus, the conventional bus bridge 20 performs data transfer between the I/O bus 26 and the memory bus 27.
As described above, in the conventional bus bridge 20 it is desirable to have the performance of data transfer enhanced. For example, Japanese Patent Laid-Open (Kokai) No. 2000-132503 discloses a data transfer device in which interface board including a target is provided with a plurality of reception buffers so that an initiator can process the data efficiently.
However, in the conventional bus bridge 20, the arrangement is made such that as circuit configuration the circuit is provided with a transmission buffer 201 and a reception buffer 202 each, so that there is caused a disadvantage in that the transmission buffer 201 and the reception buffer 202 are hardly configured to be optimum for both protocols of the memory bus 27 and the I/O bus 26.
Also, there occurs the following economical disadvantage. That is adapted for example, in the I/O bus 26 or memory bus 27, when a protocol such as bus clock or data length is changed, the conventional bus bridge 20 cannot cope with such changes. Accordingly, the entire bus bridge 20 has to be changed for a new one.
Further, generally, in processor unit such as CPU, there is known a technique in which instructions in a program are executed in disregard of the order described in the program (out of order execution) to achieve the high speed of the processing.
Also, there is known such a technique in which, in the bus bridge 20, the packets to be transmitted to the memory bus 27 are processed and transmitted with the address portion and the data portion being dealt with as separate packets.
However, in the conventional bus bridge 20, both of the I/O transmission buffer 201 and the I/O reception buffer 202 are arranged such that the data are read and written in a manner of FIFO. Therefore, the out-of-order execution cannot be carried out by the technique in which the address portion and the data portion are handled as separate packets.
Further, in the conventional bus bridge 20, there is the following problem. That is, when a virtual channel function in which a physically one I/O bus 26 is used as if pluralities of channels were virtually connected, is to be carried out, no overtaking control of packet can be effected.